电脑硬件 芯片 PC 机总线引脚定义.docx

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1、AGP总线定义AGP是AcceleratedGraphicsPort,是Intel推出的一种3D图形标准接口，它能够提供四倍于PCI的效率，AGP2X的传输速率达到533MB。有关AGP的说明可以在Int的网站上找到。引脚定义IinB面A面Spare12V5.0VSpare5.0VReservedUSB+USB-GroundGroundINTB#INTA#ClockRST#REQ#GNT#Vcc3.3VVcc3.3V0STOSTl1ST2Reserved2RBF#PIPE#3GroundGround4SpareSpare5SBAOSBAl6Vcc3.3VVcc3.3V7SBA2SBA38SB.

2、STBReserved9GroundGroundOSBA4SBA51SBA6SBA72KeyKey3KeyKey4KeyKey5KeyKey6Address31Address307Address29Address288Vcc3.3VVcc3.3V9Address27Address26OAddress25Address241GroundGround2AD_STB1Reserved3Address23C/BE3#4Vddq3.3Vddq3.35Address21Address226Addressl9Address20PUOJ)pun0j99TTSSjpp3ssjppvPSssjppt7ssjppb

3、pp,bpp3-ssjpp#T39/3THd#dd3S0PUneM9pun0j96jeds#1.ad8#d01Sbpp1.#人(Rl#1AmQ99t7PUnCM9PUno93lIdd#xaaibppbpp09ssjpp#239/368TSSjppvZtSSaIPPV8pu0j9punojg1.6AddresslOAddress97Address8C/BEO#8Vddq3.3Vddq3.39AD.STB0Reserved0Address7Address61GroundGround2Address5Address43Address3Address24Vddq3.3Vddq3.35AddresslA

4、ddressO6SMBOSMBlATA44接口ATA是ATbusAttachment的缩写，由Conner,Seagate和WesternDigital公司开发，是新版的IDE接口，ATA44接口是ATA接口再加上电源等线，主要用于便携式计算机用2.5“硬盘，在设备和主板侧的外观为44脚插针：ATA44电缆外观为：引脚定义ATA44接口的1-40脚的定义同ATA141-44的定义为：软驱接口35软驱和5软驱连线，外观为引脚定义EX0/MOTEAMotorEnableA2/DRVSBDriveSelB4/DRVSADriveSelA6/MOTEBMotorEnableB8/DIRDirectio

5、n/STEPStep2/WDATEWriteData4/WGATEFloppyWriteEnable6/TRK00Track08/WPTWriteProtect0/RDATAReadData2/SIDElHeadSelect4/DSKCHGDiskChangeIDE接口IDE是IntegratedDriveElectronics的缩写，由Compaq和WesternDigital公司开发，新版的IDE命名为ATA即ATbusAttachment1IDE接口在设备和主板侧的外观为40脚插针：IDE电缆外观为：引脚定义inNameDescription/RESETResetGNDGroundDD7

6、Data7DD8nData8DD6Data6DD9Data9DD5Data5DDlOData10DD4Data4ODDllData111DD3Data32DD12Data123DD2Data24DD13Data135DDlData16DD14Data147DDODataO三DD15IData159GNDGroundOKEYKey1n/cNotconnected2GNDGround3/IOWWriteStrobe4GNDGround5/IORReadStrobe6GNDGround7IO_CH-RDY8A1.EAddress1.atchEnable9n/cNotconnectedOGNDGrou

7、nd1IRQRInterruptRequest2/IOCS16IOChipSeIect163DAlAddress14n/cNotconnected5DAOAddressOISA总线定义ISA是IndUStryStandardArchitecture的缩写接口卡的外观引脚定义w定义说明1/I/OCHCKI/Ochannelcheck;activelow=parityerror2D7Databit71.3D6IDatabit64D5Databit55D4Databit46D3IDatabit37D2Databit2.8DlIDatabit19DO1Databit010I/OCHRDYI/OChan

8、nelready,pulledlowtolengthenmemorycycles11AENAddressenable;activehighwhenDMAcontrolsbus12A19Addressbit1913A18IAddressbit1814A17Addressbit1715A16Addressbit1616A15Addressbit1517A141Addressbit1418A13Addressbit1319A12Addressbit1220AllAddressbit1121AlOAddressbit1022A9Addressbit923A8Addressbit824A7Address

9、bit725A6Addressbit626A5Addressbit527A4Addressbit428A3Addressbit329A2Addressbit230AlAddressbit131AOAddressbit01GNDGround2RESETActivehightoresetorinitializesystemlogic35V+5VDC4IRQ2InterruptRequest25-5VDC-5VDC6DRQ2DMARequest27-12VDC-12VDC8/NOWSNoWaitState9+12VDG+12VDC10GNDGround11/SMEMWSystemMemoryWrit

10、e12/SMEMRSystemMemoryRead13/IOWI/OWrite14/IORI/ORead15/DACK3DMAAcknowledge316DRQ3DMARequest317/DACK1DMAAcknowledge118DRQlDMARequest119/REFRESHRefresh20C1.OCKSystemClock(67nsl8-8.33MHz,50%dutycycle)21IRQ7InterruptRequest722IRQ6InterruptRequest623IRQ5InterruptRequest524IRQ4InterruptRequest425IRQ3InterruptRequest326/DACK2DMAAcknowledge227T/CTerminalcount;pulseshighwhenDMAterm,countreached28A1.EAddress1.atchEnable29+5V+5VDC30OSCHigh-speedClock(70ns,14.31818MHz,50%dutycycle)31GNDGround1SBHESystembushighenable(dataavailableonSD8-15)21.A23Addressbit2331.A22Addressbit2241.A21Addressbit215